Does Qualcomm need to be a POET customer?As I read this article it really made me think of how POET could not only assure Qualcomm’s market share against Intel but could provide them with the ability to dominate in that market. It also makes me recall that Peter Copetti’s next stop after the AGM was to New Jersey which happens to be home of Qualcomm’s research facility for OFDMA wireless systems (LTE, 3G and 4G).
https://www.qualcomm.com/invention/research/locations/new-jersey
Now recall the work that POET does in this area as demonstrated by one of their patents:
Optoelectronic clock generator producing high frequency optoelectronic pulse trains with variable frequency and variable duty cycle and low jitter:
2. State of the Art
Communication systems employing digital pulse position modulation techniques have been known for some time as an attractive approach to secure communications with significant potential for very high bandwidth. It is currently being revisited with increased interest for wireless communication systems because of its high channel density with low crosstalk. More particularly, wireless communication systems operate in their specific government-granted section of an increasingly congested radio spectrum. Such congestions leads to unwanted channel interception and infringement, which is problematic particularly in military applications. Digital pulse position modulation addresses this problem by using pulse spacing as the modulation parameter to represent either a logic level "1" or a logic level "0". Each channel from a single source is assigned a unique combination of pulse spacings (as sequence). The pulses are timed according to a unique complex code to represent a logic level "1" or a logic level "0". The unique complex code is shared only by the sender and the intended receiver. The probability of anyone intercepting the signal without the code is near zero. The use of high voltage pulses provides a superb signal to noise ratio upon detection, which simplifies the receiving circuitry.
The heart of such communication systems is a voltage controlled oscillator/frequency synthesizer with a stable pulse width and spacing between pulses. Variations in such pulse width and spacing causes jitter, which limits the performance of the system by limiting the density of channels in the system. Conventional integrated circuit technologies are limited in their ability to create high frequency pulses with minimal jitter. Moreover, the voltage levels of such pulses are limited, and power dissipation is significant. Typically, the voltage controlled oscillator/frequency synthesizer is realized by some form of astable multivibrator implemented in bipolar circuitry. The time delay between pulses is provided by a varying the capacitive loading of the astable multivibrator. In such configurations, the time delay is determined by a trigger point within the astable multivibrator, which is subject to fluctuation due to noise. Reducing this noise level is a major issue in controlling the trigger point of the astable multivibrator. For example, high speed voltage controlled oscillators (such as those based on silicon germanium heterojunction bipolar transistor technology developed by IBM) are capable of switching waveforms with rise and fall times in the range of 0.5 nanoseconds. However, the high voltage levels are small (on the order of 200-400 millivolts) and the power dissipation is significant. Moreover, such devices suffer from pulse delay variability, which introduces unwanted jitter and limits the performance of the system as described above.
High frequency clock sources with low jitter are also important components to optical communication systems. Typically such systems include a high frequency voltage controlled oscillator/frequency synthesizer that generates an electrical oscillating signal having a desired frequency and amplitude level. This electrical oscillating signal is supplied to a high speed laser driver that drives a laser diode to produce an optical clock signal at the desired frequency. The optical power level of the optical clock signal is controlled by the DC level of the electrical signal generated by the laser driver that drives the laser diode. The optical clock signal produced by the laser diode is supplied to a fiber optic line or other waveguide operably coupled to the laser diode. Because such systems rely on frequency synthesis in the electrical domain, they suffer from the same problems as described above (e.g., a limited ability to provide high frequency pulses with minimal jitter).
Moreover, clocks and pulse sources are critical elements in next generation integration circuits such as digital signal processors, microprocessors, analog-to-digital converters, digital-to-analog converters, phased-locked loops and telecommunication receivers and transponders based thereon. In such applications, performance is dependent upon stability and jitter of the clock source(s).
Thus, there remains a need in the art to provide a mechanism that is capable of providing high frequency electrical and/or optical pulses with minimal jitter (e.g., where there is minimal variation of pulse width and spacing between pulses).
In addition, there is a need for such a pulse generation mechanism whereby the frequency and/or the duty cycle of the pulses can be controllably varied. These features enable the pulse frequency and/or pulse duty cycle to be varied, which is advantageous in many different applications. For example, these features can be used to generate carrier signals of varying frequency in wireless communication systems (such those utilizing digital pulse position modulation techniques as described above) and in optical communication systems. They can also be used to generate clocks signals of varying frequency and duty cycle in digital signal processors and microprocessors, which is useful for implementing power saving schemes whereby the frequency and/or duty cycle of the clock signals of the circuit are decreased in a power-saving mode. They are also useful as part of frequency synthesizers in analog-to-digital converters, digital-to-analog converters, and phased-locked loops.
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For review look at the recent article posted in the EETimes and the further clarification by the company in the comments section.
https://www.eetimes.com/document.asp?doc_id=1323892&