Submitted comment to the latest Ed Schneider SA post So this article reflects deeper research? All I see are deeper lies in an attempt to justify all the errors in your last post?
So without further delay let’s start tearing apart your new set of deceptive statements designed to justify your short position in POET. This will take some time so this will be the first of several responses.
You wrote:
2) Even with CMOS, POET GaAs (gallium arsenide) chips will be very expensive to produce compared to those of Si (silicon). The MBE (molecular beam epitaxy) multi-layering process is expensive and complex. This GaAs substrate with MBE-derived layers of InGaAs (indium gallium arsenide) is time-consuming and costly; it will not be able to compete on a cost basis with Si-based CMOS chips. It will also be very challenging to make this a repeatable, industrial-grade process for high-volume manufacturing.
The MBE process is expensive and complex?
Are you aware that the MBE that POET uses for R&D at the UCONN lab was built in 1984. Even with this old machine they can achieve target layer thickness of less than 1% deviation which is close enough to get the correct vertical cavity laser mode. The growth cycle to deposit the layers which make up the building blocks of all devices…analog, digital and optical on the same wafer takes about 7 hours with this old R&D machine at the UCONN lab. What this step actually does is simplifies the entire process. The thermal budget becomes a fraction of what takes place in current silicon CMOS processes. So when you consider that no technology can combine the devices that POET can in one monolithic chip the industry is left with no alternative but to assemble multiple chips requiring expensive manual processes and expensive testing to identify integrity of interconnects. So in reality it is the MBE that dramatically reduces the cost and enables great savings in time associated with single chip solutions along with the increases of performance and reduction of power budget and increased reliability by the removal of interconnections (reduced number of points of failure).
It is interesting that you would quote the comment provided in the EETimes article by Scott Elder but totally ignored the response by POET to those comments and the clarification? It is obvious that you do not want to provide factual information as the truth about POET technologies disruptive capabilities would not support your short position.
Below is the company response to Scott Elder’s comments:
To address some of the readers' comments regarding performance, density and cost:
- For high speed digital logic implemented using the nHFET and pHFET transistors. Comparing POET to Silicon CMOS for digital SoCs, logic performance will be 4 nodes better in power AND 3 nodes better in speed. We expect comparable if not better density as we expect to require far less buffering and upsizing of logic cells.
- For analog and mixed signal circuits. In addition to p and n HFET's higher transconductance, lower noise figure and larger linear operating range, we also have nHBT and pHBT devices with effectively zero minority carrier storage, very high gains and very fast transit times. Mixed signal performance will be better due to lower on chip switching noise, and better digital to analog isolation due to the semi insulating substrate, and the circuits in general will be smaller due to higher drive per unit size. We expect to support serial I/O at 50Gbps if not 100Gbps.
- Lastly are the optical capabilities of the POET process where our customers will have the ability to have optical I/Os on their devices along with digital and/or analog circuitry described above. We expect on chip memory to be denser and faster due to thyristor based 2-element memory cell and much better sense amplifiers.
All of the capabilities described above will allow designers of complex systems and SoC solutions to innovate in ways that have not been possible to date with existing processes. These system integration possibilities will enable lower solutions and manufacturing costs.
Looking at IC costs, one needs to consider the total cost of ownership viewpoint in making comparisons. If you look at cost/sq mm of state of the art CMOS, these numbers generally assume high fab utilization and do not amortize the cost of R&D, including NREs. The number of companies that can develop the process and manufacturing capability for state of the art CMOS can now be counted on one hand, and that is because there are only a handful of customers or vertically integrated companies that have applications where the volumes can absorb the development costs and fill the fabs. With respect to 40nm and manufacturing technology, our FEOL process is substantially simpler than an equivalent CMOS technology, and our BEOL is the same. With adoption and resultant volume scaling, we expect that the wafer costs will come down thanks to volume and manufacturing is within the capability of 4 to 6 year old toolsets. NRE costs will be significantly lower as compared to like performance silicon nodes, drastically lowering the breakeven point on a unit basis. Users of this technology will address applications that differentiate on performance capabilities or differentiate on cost due to system level partitioning and optical integration not even possible with existing technologies, and will be able to command differentiated product pricing. Bottom line is that a whole new set of business cases become possible with this technology that were previously impossible due to inaccessibility of required performance.
In summary, POET technology will not replace, but supplement CMOS in applications requiring the highest performance, integration and/or lowest power. Our vision is that many foundries will eventually offer POET Technologies processes along side of their existing processes to their existing customer base to enable solutions that are not realizable today with any other process out there