MoSys
(NASDAQ: MOSY), a leader in semiconductor solutions that enable fast,
intelligent data access for network and communications systems, today
announced the architecture for its third generation Bandwidth
Engine® family, featuring the industry's highest serial throughput
and memory access rate, optimized efficiency and scheduling for
multi-core processing, and expanded multi-cycle embedded macro
functions. The combination of size, access rate and embedded
acceleration offloads expands the packet processing performance,
addressing the simultaneous increase in both data throughput and network
intelligence for next-generation systems targeting networking
infrastructure, communications, big data and security applications.
Exponential growth in worldwide network traffic from connected devices
and cloud services is creating a need for increasingly complex network
management services that support dynamically changing applications and
workloads. The third generation Bandwidth Engine architecture delivers
unprecedented performance capability, offering over 800 Gigabits per
second (Gbps) IO performance, up to 10 billion data accesses per second,
and over 1 Gb of high access rate embedded 1T-SRAM®
memory. Used in conjunction with FPGA, ASIC or NPU based packet
processors, the new Bandwidth Engine architecture accelerates effective
throughput and expands lookup and statistics capacity to provide
flexible and scalable performance and feature enhancement.
"Our third generation Bandwidth Engine continues our commitment to
providing our customers with performance and scalability as well as the
fundamental benefits of size, power, pin count and economics,” stated John
Monson, VP of marketing for MoSys. “The core functionality of this
new architecture delivers scale in speed, access, throughput and size,
while the integration of multi-cycle offload and threading capabilities
enable a new co-processing paradigm for performance and feature
expansion."
"Given ever-increasing demand for network bandwidth and new services,
system architects are looking to offload network functions, boost
concurrent processing capabilities and improve efficiency across the
entire network," said Bob
Wheeler, principal analyst for networking at The Linley
Group. "MoSys’ third generation Bandwidth Engine architecture is driving
memory access performance to new heights. The performance of MoSys’
innovative new architecture combined with the efficiency of its open
GigaChip Interface protocol supports the access and offload acceleration
performance required to meet the needs of 100G, 400G and terabit
networks."
MoSys’ new Bandwidth Engine architecture leverages a number of key
advancements to enable unprecedented performance. The highly efficient GigaChip™
Interface has been accelerated to support up to 16 lanes running as
fast as 28 Gbps following standard OIF CEI electrical specifications.
Enhancements have been made to improve efficiency for variable sized
commands and packets to maximize effective throughput of data transfer
in both directions. For increased size, flexibility and ease of
scheduling for multi-core processors, the architecture allows for
multiple threads to be issued into extensive multi-cycle macro
processing functions or directly across the power and speed optimized
1T-SRAM array. The memory capacity has been scaled to over 1 Gb. The new
architecture also supports additional atomic read-modify-write access
capabilities to address applications such as coherent multi-threaded
access of queues and data structures, as well as n x
100GE network statistics with activity aging, running averages and
policing up to 1+ Terabits per second.
Continuing with support for carrier and enterprise class reliability
requirements, MoSys’ Bit
Safe™ Self-Test and Self-Repair technology provides an additional
safety net, maximizing system uptime through a 10 year or longer service
life requirement.
Michael
Miller, VP of technology innovation and system applications for
MoSys, will present additional details on the new third generation
Bandwidth Engine architecture in his presentation, “Intelligent Offload
Supporting Data Center Equipment at 100G+” at the Linley
Tech Data Center Conference 2014 during Session 3, entitled
Advancements in Packet Processing, from 3:10-4:40pm on February 5, 2014.
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) is a fabless semiconductor company enabling
leading equipment manufacturers in the networking and communications
systems markets to address the continual increase in Internet users,
data and services. The company's solutions deliver data path
connectivity, speed and intelligence while eliminating data access
bottlenecks on line cards and systems scaling from 100G to
multi-terabits per second. Engineered and built for high-reliability
carrier and enterprise applications, MoSys' Bandwidth Engine® and
LineSpeed™ IC product families are based on the company's patented
high-performance, high-density intelligent access and high-speed serial
interface technology, and utilize the company's highly efficient
GigaChip™ Interface. MoSys is headquartered in Santa Clara, California.
More information is available at www.mosys.com.
1T-SRAM, Bandwidth Engine and MoSys are registered trademarks of
MoSys, Inc. in the US and/or other countries. Bit Safe, GigaChip,
LineSpeed and the MoSys logo are trademarks of MoSys, Inc. All other
marks mentioned herein are the property of their respective owners.
Copyright Business Wire 2014