The Silicon Integration Initiative (Si2) announced the release of a Chip
Thermal Interface Protocol (CTIP) Standard for 3D Integrated
Circuits (3D-IC) under the auspices of the Open3D Technical Advisory
Board (TAB). The Open3D TAB is chartered to define open standards for
design data formats and interfaces to enable interoperable 2.5D and 3D
design flows.
The Chip Thermal Interface Protocol (CTIP) facilitates the exchange of
thermal design information required to integrate silicon die into 3D-IC
stacks, enabling the stack designer to simulate the thermal behavior of
the entire stack, thus ensuring that it satisfies die and stack-level
requirements. The standard does not assume that the individual die and
the complete 3D-IC stack are designed by the same team or same design
system, allowing maximum flexibility of die stack and package
integration. The CTIP standard will facilitate integration into
multi-vendor EDA tool flows used in the design of either the 2D die or
the 3D-IC stacks.
Simulating thermal behavior is critical for 3D-IC designs, as areas of
high thermal load must be equally distributed throughout the entire
stack of die to ensure proper operation in all expected conditions. The
CTIP standard provides designers with the ability to share thermal maps
and other design information, helping prevent the buildup of thermal
stress points. In the case of heterogeneous 2.5D and 3D design stacks,
where chips may be sourced by multiple IP vendors and foundries, the
need for communication of thermal information between vendors and
customers is even more critical in order to have a viable system design.
Additional working groups for Open3D TAB members include developing
standards to support:
-
Power Distribution Network to ensure that each stack in the die has
access to the required power supply characteristics (released May 2013)
-
Thermal design and analysis of an entire 3D stack, including thermal
constraints between neighboring dies (This release – the document can
be found at this link: http://www.si2.org/?page=1810)
-
Expression of design constraints into and out of the path-finding and
floorplanning stage of the overall design process
-
Stress management to ensure that no stack in the die is adversely
affected by the stack level stress hot spots or thermal gradients
-
Physical verification to facilitate stack level physical DRC
verification
-
Signal integrity to facilitate stack level electrical modeling
At the upcoming Design Automation Conference (DAC) in San Francisco,
there will be a 3D Panel: “Design for 3D: Are Standards Leading the Way
or Lagging Behind?” at 3PM, on Monday, June 2 in Room 300 at the Moscone
Center. Representatives from Qualcomm, Altera, Invensas, eda2asic, and
Helic will be speaking. The abstract is located at this link: http://www.si2.org/dac_2014/abstracts/3dpanel_abstract.php
For more information on the Open3D TAB, click here: http://www.si2.org/open3d_index.php
More information on Si2 sponsored activities, including a presentation
by Dr. Chenming Hu of UC Berkeley and a press conference with
STMicroelectronics and IBM are located at this link: http://www.si2.org/dac_2014/dac_2014_fp.php
Open3D TAB Members:
Altera (NASDAQ: ALTR), AMD (NYSE: AMD), ANSYS (NASDAQ:ANSS), Atrenta,
Cadence Design Systems (NASDAQ: CDNS), Fraunhofer Institute,
GLOBALFOUNDRIES, Helic S.A., IBM (NYSE: IBM), Intel (NASDAQ: INTC),
Invarian, Mentor Graphics (NASDAQ: MENT), Qualcomm (NASDAQ: QCOM),
R3Logic, SEMATECH, STMicroelectronics (NYSE: STM), and Texas Instruments
(NYSE: TXN).
About Si2
Si2 is the largest organization of industry-leading semiconductor,
systems, EDA and manufacturing companies focused on the development and
adoption of standards to improve the way integrated circuits are
designed and manufactured. Now in its 26th year, Si2 is uniquely
positioned to enable timely collaboration through dedicated staff and a
strong implementation focus driven by its member companies. Si2
represents over 100 companies involved in all parts of the silicon
supply chain throughout the world, www.si2.org
Copyright Business Wire 2014